Evgeni Stavinov is a system design engineer for Xilinx who holds an MSEE from USC and a BSEE from The Technion -- Israel Institute of Technology. He has more than 10 years of design experience in the areas of FPGA logic design, embedded software, and networking. Evgeni worked for CATC, LeCroy, and SerialTek designing test and measurement tools for USB, Wireless USB, PCI Express, Bluetooth, SAS, and SATA protocols. He also created OutputLogic.com -- a web portal that offers online tools for FPGA and ASIC designers -- and serves as its main developer.
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